The present invention relates to a non-volatile semiconductor memory device, in particular, a non-volatile semiconductor memory device that can maintain its data holding characteristics even though the number of writing data is increased.
A non-volatile semiconductor memory that can electrically rewrite has been proposed, using a MOS transistor of double-layered structure, which has a floating gate and a control gate. The semiconductor memory writes data by injecting electric charges from a channel through a floating gate via an insulation layer by a tunnel current. The injected electric charge is used as information storage of digital bits. It can read the information out by sensing a conductance change of a MOSFET responsive to the electric charge.
However, if, in the construction of the non-volatile semiconductor memory and by the method thereof, electric charge injection is repeated while increasing the current density in order to write data at a high speed, the abovementioned insulation film is deteriorated to increase the leakage current, and finally the data holding characteristics thereof may be worsened. The problem is described below with reference to FIG. 12 and FIG. 13.
FIG. 12 shows a memory cell matrix of a prior art non-volatile semiconductor memory and a circuit block of the major parts of the peripheries thereof.
In FIG. 12(a), reference numbers 1 and 1xe2x80x2 indicate data transfer lines, 6 and 6xe2x80x2 indicate data selection lines. These lines are disposed in the direction orthogonal to each other. Reference number 3 indicates a memory cell unit, and is provided at the intersections between the data transfer lines 1,1xe2x80x2 and data selection lines 6,6xe2x80x2.
In FIG. 12(a), four memory cell units 3 are connected to each of data transfer lines 1,1xe2x80x2, and two memory cell units are connected to each of data selection lines 6,6xe2x80x2, thereby constituting a 2xc3x974 memory cell unit matrix. Further, a latch 4 or 4xe2x80x2, which provisionally holds written data is provided at one end of the respective data transfer lines 1,1xe2x80x2.
The latches 4,4xe2x80x2 concurrently act as a sensing amplifier circuit to read out data of the memory cell units 3. Also, data lines 10,10xe2x80x2 are connected to the latches 4,4xe2x80x2 in order to transmit written and read data to a peripheral circuit and receive the same therefrom. In addition, the latches 4,4xe2x80x2 are both connected to a signal line which establishes timing to latch data. In this structure, memory cell units a11, a12 a21, a22, connected to one data transfer line such as data transfer line 1 mean memory block.
And, as shown in FIG. 12(b), a clock generation circuit 11, which adequately executes the timing and output a signal thereof is provided at the signal line 9 and data selection lines 6,6xe2x80x2. Also, hereinafter, in compliance with the practice, the direction along the data selection lines 6,6xe2x80x2 is called a xe2x80x9ccolumnxe2x80x9d, and the direction along the data transfer line 1 is called a xe2x80x9crowxe2x80x9d.
In a prior art circuit shown in FIG. 12, where data are written in the memory cell units a11 and b11, it is necessary to apply an electric potential to the data transfer lines 1,1xe2x80x2 to which the memory cell units a11 and b11 are connected. Therefore, the output voltage of the data latches 4,4xe2x80x2 is adjusted so as to become a voltage value responsive to writing data. At the same time, a program voltage Vpgm that has a larger potential difference than the potential of the data transfer line in which writing is carried out is applied to the data selection line 6. At this time, the program voltage Vpgm is applied so that a high voltage enough to cause an electric current to flow in the abovementioned insulation film (the gate insulation film of the MOSFET) of a memory element located in the memory cell unit 3 is applied. At this time, the program voltage Vpgm is made pulse-like while having a sufficient duration of time of carrier injection.
In this case, it is requested that data of the memory cell unit a11 is not erroneously written in a non-selected memory cell unit, for example memory cell unit a21, connected to the same data transfer line 1 as that of the memory cell unit a11. Therefore, it is necessary that the potential of the data selection line 6 connected to the non-selected memory cell unit a21 approaches the potential of the data transfer lines 1,1xe2x80x2 further than the abovementioned program voltage Vpgm. Accordingly, it is impossible to write optional data in memory data of a plurality of columns. That is, the number of lines in which data can be written per program pulse is one column.
FIG. 13 shows a flowchart of the non-volatile semiconductor memory, including a verification motion that can carry out writing of data in a plurality of columns, for example, two columns.
A sequence of writing data in memory cell units a11, b11 of the first column is comprised of a step (S1) for loading data to be written in the first column in the latches 4,4xe2x80x2, a step (S2) for applying a program pulse to the data selection line 6, to which the memory cell units a11 and b11 of the first column is connected, a step (S3) for storing the result of judgment of a threshold of the memory cell units from and in which the data of the first column is read and written, into the data latches 4,4xe2x80x2, a step (S4) for judging the result of judgment about whether or not writing is completed in all the memory cell units of the first column, and a step (S5) for re-establishing a program pulse voltage and a pulse width in a case where the result of the judgment in the step S4 is No. Also, hereinafter, the sequence in which only the column differs is expressed with a dash (xe2x80x2) attached.
Therefore, in a case where data are written in a plurality (for example, n columns) of memory cell units, it is necessary to carry out the same sequence as the abovementioned sequence from S1 through S5 xe2x80x9cnxe2x80x9d times in time series as described in steps S1xe2x80x2 through S5xe2x80x2. In this case, where it is assumed that the times necessary for motions in S1, S2, S3, and S4 are TS1, TS2, TS3 and TS4, the time required to write all the data is at least nxc3x97(TS1+TS2+TS3+TS4). Therefore, if the number of columns is increased xe2x80x9cnxe2x80x9d times, the writing time is accordingly increased xe2x80x9cnxe2x80x9d times.
Herein, in order to decrease the time required to write all the data, there is a method of decreasing the program time TS2 that takes most time. But, if, with respect to an electric charge required to write, the writing current is increased, low field leakage of the tunnel insulation film is increased further than the writing current is decreased by lengthening the program time (K. Naruke, 1988, IEEE Technical Digest IEDM p.424).
Also, if a silicon oxide film is used as a gate insulation film of the memory element, there arises another problem that a stress leakage current flows to the gate insulation film. When writing, the gate insulation film may receive a larger field stress than 10 MV/cm in order to flow an FN tunnel current to. By receiving the field stress, a leakage current flows at a low field that is, for example, 5 MV/cm or less. The leakage current may be increased further than the value that can be presumed by the FN tunnel current. This is a stress leakage current.
For this reason, in a non-volatile semiconductor memory in which data are repeatedly written and deleted, a leakage current flow since an electric field resulting from electric charge accumulation is applied between a floating gate and a substrate in a state where an electric charge is held, and the electric charge is liable to disappear. In a non-volatile semiconductor memory, it is requested that information is retained and held in a high temperature of at least 85xc2x0 C. for ten years, it was necessary to prevent the electric charge from disappearing with no power source provided.
As described above, in a non-volatile semiconductor memory of prior art structure, where data are written in a plurality of columns, there was a problem that the data writing time was greatly increased. Also, increasing current of writing data in order to speed up the data-writing make the stress leakage current increase, resulting in a problem of worsening the data holding characteristics of a memory.
The invention was developed in view of solving the problems, and it is therefore an object of the invention to provide a non-volatile semiconductor memory device that improves the data writing speed, and at the same time, can prevent the data holding characteristics from being worsened.
In order to solve the problems, the present invention provides a non-volatile semiconductor memory device comprising:
a first data transfer line;
a plurality of a first memory cell unit having a non-volatile semiconductor memory cell, connected to the first data transfer line;
a first data selection line connected to the each first memory cell unit;
a second data transfer line;
a plurality of a second memory cell unit having a non-volatile semiconductor memory cell, connected to the second data transfer line;
a second data selection line connected to the each second memory cell unit;
a data holder connected to the first data transfer line;
a switching element inserted between the first transfer line and the second data transfer line;
wherein, when writing data, the switching element is shut off, and one of the first data selection lines and one of the second data selection lines are simultaneously selected.
It is preferred that the transfer line and the data selection line are disposed orthogonal to each other and one row of a memory block having the memory cell units and the switching element connecting to the first transfer line is juxtaposed in a plurality rows in the direction of the data selection line and a memory matrix composed of the rows of the memory block and a control line disposed to connect to the switching element in parallel to the selection data line is further comprised.
It is preferred that the data holder contains a flip flop formed by a semiconductor element.
It is preferred that the data holder is provided with a plurality of circuits which provisionally hold written data.
It is preferred that the memory cell unit includes a field effect transistor provided with at least an electric charge accumulating layer and a control gate.
It is preferred that the field effect transistor uses an FN tunnel current for writing.
It is preferred that wherein the electric charge accumulating layer contains polysilicon or silicon nitride film.
It is preferred that the memory cell unit is composed of a NAND cell unit having a plurality of memory cells connected in a series.
It is preferred that a data holder connected to the second data transfer line is further comprised and the second data holder connected to the second data transfer line is composed of a fewer number of transistors than that of the data holder connected to the first transfer line.
It is preferred that the data holder connected to the first data line is composed of a sensing amplifier.
The present invention provides a non-volatile semiconductor memory device comprising:
a data transfer line;
a first memory cell unit and a second memory cell unit having a non-volatile semiconductor memory cell, connected to the data transfer line;
a first data selection line connected to the first memory cell unit;
a second data selection line connected to the second memory cell unit;
a data holder connected to the first data transfer line;
a first switching element inserted between the first transfer line and the first memory cell unit;
a second switching element inserted between the second line and the second memory cell unit;
wherein, when writing data, at least one of the fist switching element and the second switching element is shut off, and the first data selection line and the second data selection line are simultaneously selected.
It is preferred that the data transfer lines and the data selection lines are disposed orthogonal to each other and one row of a memory block having the memory cell units and the switching element connecting to the transfer line is juxtaposed in a plurality rows in the direction of the data selection line and a memory matrix composed of the rows of the memory block and a control line disposed to connect to the switching element in parallel to the data line is further comprised.
It is preferred that the first switching element and the first memory cell unit are formed on the same well, and the second switching element and the second memory cell unit are formed on the same well.
It is preferred that the data holder contains a sensing amplifier.
It is preferred that the data holder is made up of a flip flop formed by a semiconductor element.
It is preferred that the memory cell unit includes a field effect transistor provided with at least an electric charge accumulating layer and a control gate.
It is preferred that the field effect transistor uses an FN tunnel current for writing.
It is preferred that the electric charge accumulating layer contains polysilicon or silicon nitride film.
It is preferred that the memory cell unit is composed of a NAND cell unit having a plurality of memory cells connected in a series.
It is preferred that the data holder is provided with a plurality of circuits which provisionally hold written data. uses an FN tunnel current for writing motions.
According to the invention, a switching element is inserted between the first data transfer line and the second data transfer line that are separated from each other, and by turning off the switching element when programming, it becomes possible to select one of the first data selection lines and one of the second data selection lines at the same time in writing data.
Therefore, in a case of writing data in a plurality of columns, the time of writing data can be decreased to half without changing the writing time per memory cell unit. In a case where the number of dividing the data transfer lines is further increased, the data writing data can be reduced to one-(the number of dividing the data transfer lines)th at maximum. Accordingly, it is possible to write data at a higher speed, wherein consumption power of program pulses can be reduced. It is especially effective in a device, the writing speed of which is slow, like an EEPROM of a double gate structure.
Also, all the data writing time can be shortened by increasing the number of dividing columns, whereby it is possible to lengthen the writing time per cell. Thereby, the data writing current to write the same electric charge amount can be decreased, whereby it is possible to prevent the stress leakage current that causes consumption power to increase, and causes the data holding characteristics to be worsened.
Further, since it is possible to reduce the stress leakage current, the gate insulation film of a non-volatile semiconductor element can be further thinned, and the programming voltage in writing can also be decreased. Therefore, the area of a booster circuit to generate the programming voltage can be reduced, and the area of transistors can be reduced. Accordingly, chip area can be further decreased. Still further, power consumption can be decreased in line with a lowering of the programming voltage.
Also, in comparison with a case where a sensing amplifier is formed with respect to the respective separated transfer lines instead of a switching element as the data transfer line switch, the number of transistors can be reduced, and the circuit occupied area can also be reduced.
Still further, such a construction that does not require any power source line may be employed as the switching element. No wiring layer and contact are required to wire the power source in the memory matrix area, and it is possible to form a circuit with the same wiring construction as that of the prior arts.
In addition, since a plurality of circuits which provisionally hold written data are formed in respective sensing amplifiers, a data-transfer speed is faster and the wiring of the structure is shorter than the structure that transmits data from the peripheral data buffer to the sensing amplifiers from time to time in writing. So, the consumption power can be further decreased.
As described above, according to the invention, it is possible to reduce the data writing time by 1/(the number of divisions of a data transfer line) at maximum without changing the writing time per cell in a case of writing data in a plurality of lines. Therefore, higher speed writing can be carried out, and it is possible to reduce consumption power to form a program pulse.
Also, the total data writing time can be decreased by increasing the number of divisions of columns, whereby the writing time per cell can be lengthened. Therefore, the data writing current to write the same electric charge can be decreased, it is possible to prevent the device from deteriorating due to stress leakage, consumption power from increasing, the data holding properties from being worsened.
Further, since the stress leakage can be reduced, it is possible to further thin a tunnel insulation film of a memory cell, and the program voltage in writing can be reduced. Accordingly, since the area of a voltage boosting circuit to generate a program voltage can be reduced, and a small transistor only durable to the lower program voltage can be used, a chip area can be further reduced.
Also, in comparison to a case where a sensing amplifier is used for the respective divided data transfer lines instead of the data transfer line switches, the number of transistors can be decreased, resulting in a decrease in the circuit area. Still further, since the data transfer line switches can use a construction that does not need power source wires, no wiring layer and contact are required in the memory matrix area for power source wiring, wherein circuits can be constructed in the same wiring configuration as that of prior art examples. Further, a plurality of circuits that provisionally hold writing data are formed in the respective sensing amplifiers. Therefore, this is higher in speed than in a case where data are transferred from a peripheral data buffer to sensing amplifiers from time to time when executing writing, and the wiring length thereof is shorter. Therefore, consumption power can be reduced.